A Closer-to-Brain Heterosynaptic Learning Rule for Spatiotemporal Spike Pattern Detection with Low-Resolution Synapse

The brain is believed to process information efficiently in a different manner from deep learning-based artificial intelligence (AI). Brain-like next-generation AI is gaining attention owing to its potential to perform human-like, highly adaptive, robust, and power-efficient computation. To realize such AI, one crucial approach is the bottom-up implementation of the neuronal systems, capturing their electrophysiological characteristics in electronic circuits. However, this neuromorphic approach generally focuses on simplified neuronal models that do not refer to many biological findings. Developing closer-to-brain models is a natural direction that serve as a fundamental computing model for next-generation AI. One of the constraints of neuromorphic circuits is the bit resolution of synaptic efficacy memory, as the memory footprint scales with it precision. Although low-resolution synaptic efficacy is essential for minimizing memory circuit footprint and energy consumption, it generally leads to performance degradation in many tasks such as the spatio-temporal spike pattern detection. This study proposed a closer-to-brain learning rule that incorporates heterosynaptic plasticity (HP) induced by glutamate spillover. It is demonstrated that our model mitigates the performance degradation associated with low-bit resolution synaptic efficacy, achieving the pattern detection success rate with 3-bit resolution synaptic efficacy, which is comparable to 64-bit floating-point precision. Furthermore, the findings of the study indicate that HP based model accelerates the convergence of the synaptic effcacy and effectively potentiates the synapses relevant to the pattern detection while suppressing irrelevant ones, thereby promoting a bimodal distribution of synaptic efficacies. These findings may provide a basic framework for constructing an energy-efficient, brain-like next-generation AI that maintains high performance under hardware constraints.